1. Field of the Invention
The present invention relates generally to a circuit for and a method of providing phase synchronization and, more particularly, to a circuit for and a method of establishing phase synchronization of a horizontal synchronization signal, employed in a video signal receiver such as a TV (a television receiver), an LCD-TV (a liquid crystal display television receiver), or a VTR (a video tape recorder). More specifically, it relates to a circuit for and a method of ensuring establishment of horizontal synchronization even if employed for a video receiver having a matrix type video display such as a liquid crystal display with different numbers of pixels on a line.
2. Description of the Background Art
There is a liquid crystal panel as a small and thin video display with low power consumption. First of all, a brief description will be given on a configuration and an operation of a video signal reproducing apparatus employing this liquid crystal panel. FIG. 1 shows a schematic configuration of a whole television receiver employing the liquid crystal panel as a display device. The configuration shown in this FIG. 1 is, for example, disclosed in Japanese Pat. Laying Open Gazette (Kokai) No. 57-41078.
Referring to FIG. 1, a liquid crystal panel 101 includes liquid crystal pixels 100 arranged in m rows and n columns. The liquid crystal pixels 100 each include a switching transistor 102, a charge holding capacitor 103 and a liquid crystal element 104. Gate lines Gl-Gm are provided for selecting a particular row of the liquid crystal pixels. Source lines Sl-Sn are provided for selecting a particular column of the liquid crystal pixels. The respective switching elements 102 has a gate connected to the gate line Gi (i=1-m) and one conduction terminal (a source) connected to the source line Sj (j=1-n).
A row driver 105 and a column driver 106 are provided to drive the liquid crystal panel 101. The row driver 105 sequentially selects the gate line Gi one by one in response to a control signal from a control signal generator 117. The column driver 106 includes a shift register 107, a sample and hold circuit 108 and an amplifier 109. The shift register 107 formed of unit shift registers of n stages generates a signal for defining operation timing of the sample and hold circuit 108 in response to the control signal from the control signal generator 117. The sample and hold circuit 108 samples and holds video signals (R, G and B) from a video detector 114 in response to clock signals from the shift register 107. This sample and hold circuit 108 includes n unit sample and hold circuits provided corresponding to the source lines Sj. The amplifier 109 amplifies video information held by the sample and holds circuit 108 to transmit the same onto respective source lines Sj.
There are provided an antenna 110 for receiving video signals, a tuner 112, an intermediate frequency amplifier 113, the video detector 114, an audio processing circuit 115, and a loudspeaker 116. The tuner 112 selects a frequency band of a desired channel from the received video signals. The intermediate frequency amplifier 113 converts the video signals selected through the tuner 112 into a signal of intermediate frequency and amplifies the same to be transmitted to the video detector 114. The video detector 114 detects a video signal from a composite video signal converted into this intermediate frequency, and also separates an audio signal from the video signal to supply the same to the audio processing circuit 115. The audio processing circuit 115 detects and reproduces this audio signal to supply the same to the loudspeaker 116. The video signal from the video detector 114 is applied to the sample and hold circuit 108.
The control signal generator 117 separates a synchronization signal (a horizontal and vertical signal) from the video signal received from the video detector 114 and derives a signal required for driving the rows and columns of the liquid crystal panel 101. An operation of the circuit will be briefly described.
First, the operation of the row driver 105 will be described with reference to FIGS. 2. A video signal shown in FIG. 2 (A) is applied from the video detector 114. The video signal has a vertical synchronization signal period T1, a vertical fly-back period T2 and a video signal period T3. The video signal period T3 includes horizontal synchronization signals. The control signal generator 117 generates a signal (FIG. 2 (B)) indicating initiation of one field in response to the first horizontal synchronization signal after the vertical period T2 is completed. Accordingly, the initiation of the one field is detected. The control signal generator 117 subsequently generates a clock signal (FIG. 2 (C)) of a period 1H (H: one horizontal scanning period). In response to this clock signal (a scanning clock signal), the row driver 105 generates signals (FIG. 2 (D) to (F)) for sequentially raising the gate line Gj in potential. Accordingly, only a single gate line Gi is selected during one horizontal scanning period. The switching transistors 102 connected to this particular row (the gate line Gi) are turned on during a horizontal fly-back period, so that the pixel information transmitted onto the source lines Sl-Sn is transmitted onto the respective liquid crystal elements 104.
Meanwhile, an operation waveform diagram of the column driver 106 is as shown in FIGS. 3. The column driver 106 repeats the same operation for each 1H period. The video signal in the 1H period, as shown in FIG. 3 (A), includes a horizontal synchronization signal period and horizontal fly-back period T4, and a period T5 during which a video information is transmitted. First of all, the shift register 107 is supplied with a signal corresponding to the horizontal synchronization signal of the video signal as shown in FIG. 3 (B), and as a transfer clock pulse, a clock pulse having a frequency of the period T=T5/n' (the n' represents the number of pixels connected to a single row), or T=(T4+T5)/n, as shown in FIG. 3 (C). Accordingly, as shown in FIGS. 3 (D) to 3(F), clock signals sequentially shifted by T in the phase are output from an output of each stage of the shift register 107. The clock signals (FIGS. 3 (D) through 3 (F)) from the shift register 107 are applied to the sample and hold circuit 108. In response to the clock signals, the sample and hold circuit 108 samples the video signal derived from the video detector 114 and holds the same during the 1H period. Accordingly, information corresponding to a row of pixels is held in the sample and hold circuit 108. This pixel information is in parallel transmitted via the amplifier 109 onto the source lines Sl-Sn.
In order to hold a row of the pixel information in the sample and hold circuit 108 as described above, it is necessary to generate clock signals with the frequency n times f.sub.H (f.sub.H =1/H) which are synchronized in phase with a received synchronization signal.
In the case that the number of the pixels in a row of the liquid crystal panel 101 is fixed, each of the clock signals generated by the control signal generator 117 may be selectively generated corresponding to the number of the pixels. However, in order to configure a general-purpose control signal generator to be employed for a liquid crystal panel with various numbers of the pixels, it is necessary to employ a circuit configured in consideration of changes in the number, n, of the pixels in a row.
FIG. 4 shows an example of a conventional circuit configuration for generating horizontal synchronizing clock signals which can be employed for various kinds of the liquid crystal panels. One of ICs (integrated circuits) for horizontal phase synchronization having such configuration as shown in FIG. 4 is .mu.pD6109G, a product of by NEC (Nihon Electronics Corp).
Referring to FIG. 4, a conventional horizontal phase synchronizing circuit includes a synchronization separating circuit 14 at its input stage. The synchronization separating circuit 14 receives a video signal via a coupling capacitor C5 to extract a synchronization signal (horizontal and vertical). The horizontal phase synchronizing circuit further includes a first PLL (Phase Locked Loop) loop and a second PLL loop.
The first PLL loop includes a first phase comparator 16, a first lowpass filter 18, an adjuster 20, a first voltage control type oscillator 22, and a 1/2 frequency divider 24. The phase comparator 16 compares in phase a horizontal synchronization signal from the synchronization separating circuit 14 with a signal of a frequency 15.73KHz from the 1/2 frequency divider 24. The phase comparator 16 is of pulse width detecting type for only comparing the phases of applied signals and has a characteristic immune to noise.
The first lowpass filter 18 includes capacitors C1 and C2 and resistors R1 and R2. The resistor R2 is provided between a terminal PCO and a node N1. The resistor R1 and the capacitor C2 are provided in series between the node N1 and a ground potential. The capacitor C1 is provided in parallel to a series body of the resistor R1 and the capacitor C2. The lowpass filter 18 removes noises included in an output signal of the phase comparator 16 and generates a direct current control voltage.
The adjuster 20 includes resistors R3 and R4 and a variable resistor VR1. The resistor R3 is provided between an output of the lowpass filter 18 and a node N2. The variable resistor VR1 and the resistor R4 are provided in series between the node N2 and the ground potential. This adjuster 20 has a function of controlling an oscillation phase of the voltage control type oscillator 22. That is, adjustment of a resistance value of the variable resistor VR1 adjusts advancing or delaying in phase of an output signal of the voltage control type oscillator 22.
The voltage control type oscillator 22 oscillates with a frequency twice as large as the horizontal scanning frequency (15.73KHz). The 1/2 frequency divider 24 frequency-divides, by a factor of 2, an output of the first voltage control type oscillator 22 to output a quasi-horizontal synchronization signal f.sub.H to the phase comparator 16.
It is known that the phase comparator 16 which is of the pulse width detecting type as described above, has an output characteristic having a plurality of slopes (S curves) as shown in FIG. 5. In this FIG. 5, the abscissa designates an input signal frequency, and the ordinate designates an output voltage. f0 represents a reference signal. As seen from this figure, the phase comparator 16 provides an output voltage with the same output characteristics also when the input signal frequency to the phase comparator becomes twice or three times the frequency of the reference signal (the horizontal synchronization signal). Therefore, the first PLL loop has lock ranges corresponding to the respective S curves, and thus the first voltage control type oscillator 22 shown in FIG. 4 sometimes oscillates with the frequency twice or three times that in a normal time to become stable.
In order to prevent the first PLL loop from being stable in the frequency band other than that of the reference signal, in the manufacture of the integrated circuit IC, the oscillation frequency range of the first voltage control type oscillator 22 is set to the range of the frequency from f1 to f0 shown in FIG. 5.
The second PLL loop of the horizontal phase synchronizing circuit includes a phase/frequency comparator 26, a second lowpass filter 28, a second voltage control type oscillator 30 and a programmable counter 32. The phase/frequency comparator 26 compares in phase and frequency a horizontal scanning signal from the 1/2 frequency divider 24 with an output of the programmable counter 32. The second lowpass filter 28 includes a resistor R5 and a capacitor C3. The resistor R5 and capacitor C3 are connected in series between a terminal PFCO and the ground potential. The second lowpass filter 28 removes undesirable high frequency components such as noise components included in the phase/frequency comparator 26, and provides a direct current voltage signal only indicating a result of this comparison so as to apply the same to a voltage control terminal VCOH of the second voltage control type oscillator 30. The second voltage control type oscillator 30 having a large oscillation frequency range oscillates normally with the frequency n times the horizontal scanning frequency. The programmable counter 32 frequency-divides, by a factor of n, an output of the second voltage control type oscillator 30 to derive a signal with the horizontal frequency and transmit the same to the phase/frequency comparator 26, and also applies this n.multidot.f.sub.H (f.sub.H is a quasi horizontal scanning frequency signal) to a programmable logic array 33. The programmable logic array 33 provides a horizontal driving clock signal HCLOCK for driving the column driver 106 shown in FIG. 1. The n corresponds to the number of the pixels in a row. Therefore, the value of the n varies depending on the varied number of the pixels of the liquid crystal panel. The oscillation frequency band of the second voltage control type oscillator 30 is designed to have a large width so as to correspond to the various kinds of the liquid crystal panels.
The phase/frequency comparator 26 compares not only the phases but also the frequencies. This comparator 26 has an output characteristic having only a single slope (an S curve) as shown in FIG. 6. In the FIG. 6, the abscissa indicates an input signal frequency, and the ordinate indicates an output voltage. Since the phase/frequency comparator 26 also functions with a frequency error detector, as apparently seen from FIG. 6, the second voltage control type oscillator 30 does not oscillate with the frequency twice or three times the frequency in the normal time (nf.sub.H) That is, the second PLL loop has only one lock range so that it can oscillate at a stable state with a desired oscillation frequency.
The conventional horizontal phase synchronizing circuit, shown in FIG. 4 as described above requires two comparators 20 and 30.
It can also be considered, in order to reduce the comparators to only one, that an output of the synchronization separating circuit 14 is directly applied to the phase/frequency comparator 26. However, the following problems occur in such configuration as above. That is, in receiving a strong electric field signal as shown in FIG. 7 (a), the output of the synchronization separating circuit 14 does not include noises, thereby obtaining a stable oscillating signal synchronized in phase with a horizontal synchronization signal. However, in receiving a weak electric field signal as shown in FIG. 7 (b), the output of the synchronization separating circuit 14 includes noises, so that an output of the phase/frequency comparator 26 is affected adversely by the noises, and thus the oscillation frequency of the voltage control type oscillator is fixed to its upper limit value or lower limit value. This causes a problem that the oscillating signal synchronized in phase with a desired horizontal synchronization signal cannot be obtained.
Even in a case that the horizontal synchronization signal including noises in receiving the weak electric field signal is input to the phase comparator 16 immune to noises, the phase comparator 16 outputs noise components due to a random noise. However, since the lowpass filter 18 cancels the noise components, it resultantly outputs only phase comparison components with regularity of the normal horizontal synchronization signal and the quasi horizontal synchronization signal. Thus, the voltage control type oscillator 22 oscillates with a desired oscillation frequency (31.5KHz) in the first PLL loop, resulting in a quasi horizontal synchronization signal having the same frequency and phase as the horizontal synchronization signal.
Furthermore, malfunction is caused by applying directly to the phase/frequency comparator 26 the horizontal synchronization signal including the noise in receiving the weak electric field signal shown in FIG. 7 (b). Therefore, it is considered to remove the noise causing this malfunction. That is, by passing the horizontal synchronization signal from the synchronization separating circuit 14 through a bandpass filter having its center frequency of 15.73KHz, the horizontal synchronization signal with its noise components removed, shown in FIG. 7 (c), may be applied to the phase/frequency comparator 26. In this configuration, however, an output signal of the bandpass filter is shifted by .DELTA.T in time due to the filter processing as shown in FIG. 7 (c). That is, the phase of an output signal of the oscillator 30 is shifted by this .DELTA.T. Since the horizontal clock signal for horizontally driving the liquid crystal panel is synchronized in phase with an output of the voltage controlled oscillator 30, the horizontal position of the picture reproduced on the screen is deviated.
It is also considered to estimate or calculate the value of this .DELTA.T and to correct the deviation of this horizontal position. However, this estimation is annoying and difficult because it requires consideration of a random noise, the deviation in the delay time .DELTA.T in the bandpass filter and the deviation in signal widths of the received horizontal synchronization signal, (the output of the bandpass filter) due to noises.
The foregoing Japanese Pat. Laying Open Gazette No. 57-41078 discloses a method of generating a horizontal driving pulse in synchronization in phase with the horizontal synchronization signal in a matrix type television.
Moreover, Japanese Pat. Laying Open Gazette No. 57-8161 similarly discloses a method of providing a signal synchronized in phase with the horizontal synchronization signal by employing a PLL loop, as a horizontal driving pulse signal of a liquid crystal matrix display panel.